Professor Thomas Skotnicki

Professor Skotnicki graduated from the Faculty of Electronics, Warsaw University of Technology. He received his PhD in the Institute of Electron Technology in Warsaw and the „Habilitated for Directing Research” degree in INPG Grenoble. In 2007 he received the Professorship from the President of Poland. Currently Professor Skotnicki works as a Director for Advanced Instruments' Program in STMicroelectronics (Crolles, France), he teaches in Ecole Polytechnique Federale in Lausanne. His academic teaching record consists of lectures at the Institut National Polytechnique in Grenoble, as well as supervising about 20 doctoral dissertations.

Professor Thomas Skotnicki is a co-author of The International Semiconductor Roadmap for Semiconductors - a periodically updated publication, describing development directions and research tasks for the global semiconductor industry. Additionally he is an author or co-author of approximately 300 articles and a holder of about 50 patents. In 2001 - 2007 he served as an editor to the IEEE Transactions on Electron Devices.

Professor Skotnicki will be hosted at the Warsaw University of Technology between October 30, 2009 and November 30, 2009 performing research which would lead to better understanding and consistence optimization between particular structural features of an active device (such as MOS transistors created using „bulk” and „FD SOI” technologies) and project circuit optimization involving power consumption, productivity and occupied space. The research will be conducted in a real digital circuit context represented by low power consumption projects designed for the 20nm CMOS technology. Factors such as minimum voltage, temperature dependency, effectivity of base polarization techniques towards the source. The main focus will be directed towards studies of various technologies („bulk”, „FD SOI” and others, i.e. regular matrix devices) and how they influence computable productivity of digital circuits. Further, research results should enable to develop a guideline for designing circuit topography, making it possible for cell designers to maximized use of technology's possibilities, which would lead to global project and technological process optimization.

For this purpose STMicroelectronics will provide examples of logical critical paths in digital projects. Conclusions will be made according to the most beneficial technologies and related recommendations regarding circuit topographies.

Professor Wiesław Kuźmicz and Professor Stanisław Janeczko will be hosting professor Thomas Skotnicki at the Warsaw University of Technology.